1. Field of the Invention
Embodiments of the present invention generally relate to communication transceivers, and more particularly to combining transmit and receive amplifiers in complementary metal oxide semiconductor (CMOS) transceivers.
2. Description of the Related Art
A transceiver is a well-known circuit containing a transmitter and a receiver, which are capable of transmitting and receiving communication signals, respectively. Conventionally, the transmitter's analog front end contains a power amplifier (PA) that provides the last stage of amplification of the signal to be transmitted, while the receiver's analog front end contains a low noise amplifier (LNA) that provides the initial stage of amplification of the signal to be received. In a wireless communication system, the transmit PA and receive LNA may each couple to a shared antenna through separate impedance matching networks and a common transmit/receive (T/R) switch through which both the high power transmit differential signal and the low power receive differential signal pass.
FIG. 1 illustrates a block diagram of a prior art wireless transceiver analog front end 100 coupled to a common antenna 105 through separate transmit and receive paths. The internal transmit PA 101 connects through an external differential matching network 102 and a differential to single-ended balun 103 to a T/R switch 104. In the transmit mode, the T/R switch 104 connects the transmit differential signal through node 109 to the antenna 105. Similarly the internal LNA 106 connects through a separate external differential matching network 107 and a separate differential to single-ended balun 108 to the same T/R switch 104. In the receive mode, the T/R switch 104 connects the receive differential signal to node 110 from the antenna 105. The impedance seen at the output of the transmit PA 101 toward the board is set relatively low by the external matching network 102 to maximize power transfer from the transmit PA 101 to the external balun 103. The impedance seen at the input of the LNA 106 toward the board is usually set relatively high by the external matching network 107 to maximize signal gain from the external balun 108 to the receive LNA 106. With separate transmit and receive paths, the input of the LNA 106, usually designed using lower voltage “core” transistors, is isolated by the T/R switch 104, and thereby protected, from the high voltages generated at the output of the PA 101, usually designed using higher voltage I/O transistors. While the separate external transmit and receive paths provide good signal performance and isolation, they disadvantageously add system cost and require separate transmit and receive 111, 112 I/O pins on the transceiver chip for each RF connection to an external antenna.
FIG. 2 illustrates a prior art wireless transceiver analog front end 200 that integrates the multiple impedance matching networks and T/R switch of the prior art of FIG. 1 onto a CMOS device. This integrated design reduces both the device's pin count, by decreasing the number of input/output (I/O) pins, and the wireless system's cost and board area but adds on-chip complexity. In particular, the wireless transceiver analog front end 200 includes a T/R switch 208 and a pair of transmit and receive impedance matching networks 202, 207 in the CMOS device. For the transmit path, a transmit PA 201 couples to an antenna 205 through an internal transmit impedance matching network 202, a shared external impedance matching network 203 and an external balun 204. For the receive path, a receive LNA 206 couples to the antenna 205 through an internal receive impedance matching network 207, the external impedance matching network 203 and the external balun 204. In the transmit mode, the integrated T/R switch 208 connects to node 209 (pa on) thereby shorting the LNA 206 inputs. The LNA impedance matching network 207 will appear as an open circuit to the transmit PA 201, in transmit mode, and thus will not distort the PA output transmit differential signal at nodes 211. In the receive mode, the integrated T/R switch 208 connects to node 210 (Ina on) enabling the LNA receive path, while the transmit PA 201 simultaneously powers down, thus presenting a small load that does not disturb the LNA input receive differential signal at nodes 211. Advantageously in this design, integrating the T/R switch 208 and the impedance matching networks 202, 207 enables sharing a single pair of I/O pins 211 for both transmit and receive paths rather than using two separate pairs of I/O pins 111, 112 as required by the transceiver analog front end 100 of FIG. 1. The impedance of each of the matching networks 202, 203, 207 may be set individually to achieve a desired power transfer. Disadvantageously in this design the internal low impedance LNA matching network 207, which may be built from low-Q inductors, may be lossy and also sensitive to adjacent digital signals and thus prone to introduce noise spurs into the low level receive differential signal input to the LNA 206 thereby lowering receiver performance.
Therefore, what is needed is a transceiver analog front end design that integrates the transmit power amplifiers and receive low noise amplifiers, eliminates the internal impedance matching networks and uses only one pair of I/O pins in a wireless communication system thereby reducing chip cost, system cost and system board area yet maintaining the higher receiver performance of conventional designs.